Venkata Sai Charan Jammi
Course: M.Tech.
Batch: 2021- 2023
Area of Research: Leakage Power Optimization in Physical Design stages.
I am currently pursuing M.Tech. in VLSI Design, School of VLSI and Embedded System, NIT Kurukshetra and joined Siemens EDA in July 2022 as intern. My current internship work is focused on the leakage power optimization starting from placement stage till routing stage without any compromise in Timing QoR.
Background: B. Tech. in Electronics and Communication Engineering.